1. Field of the Invention
The present invention relates to DRAM cells, and more particularly, to DRAM cells that can comprise three transistors in a 4F2 cell area.
2. Description of the Prior Art
In the field of semiconductor memory, it is desirable to have as many devices in as small an area as possible. A number of structures and layouts are proposed in order to achieve this purpose. For example, some DRAM cells use stacked transistors to increase the number of transistors that can occupy a particular area. FinFET technology is another example of a particular technology that aids in the miniaturization of DRAM cells. FinFETs comprise two fins on either side of a trench where each fin has a source and drain on each side, and a gate formed over the fin.
A recent development in semiconductor technology is the miniaturization of a DRAM memory cell down to an area of 4F2, where F is a standard parameter used in the art. A typical cell will consist of a read word line, a write word line, a trench capacitor and a bit line/digit line for carrying charge. In most DRAM operations, the read cycle is destructive, meaning that the data will automatically need to be written back after the read has taken place. For a CMOS image sensor, however, the read cycle is not destructive. This allows the read process to take place very quickly. A CMOS image sensor, however, requires three transistors, which has an impact when miniaturization is desired.
It is therefore an objective in the art to create a high density DRAM that still occupies a minimum area.